The present invention relates to a data processor such as a microprocessor or a microcomputer. More particularly the present invention relates to a method and apparatus for use in a data processor to cause the data processor to attain high-speed performance while maintaining software compatibility.
There are varieties of architectures for microprocessors. For example, there are microprocessors of CISC (Complexed Instruction Set Computer), RISC (Reduced Instruction Set Computer) and VLIW (Very Long Instruction Word) (or LIW (Long Instruction Word)) types to name a few.
With, for example, 8 or 16 bits as a minimum instruction length unit, the CISC type microprocessor forms an instruction system (an instruction set) with a variable-length instruction format of integral multiples of the minimum instruction length unit. In this case, a maximum instruction length ranges from 48 bits to 64, 80 bits and so forth. Due to microprogrammed control with a large number of instructions constituting an instruction set and due to the fact that a plurality of processes are performed by one instruction and the instruction length is variable, the amount of required hardware is large, so that the architecture is said to have a drawback in seeking high-speed performance. Motorola""s 680X0 and Intel""s 80X86 are typical examples of the CISC type microprocessor.
A key to attaining such high-speed performance, the RISC type microprocessor has been introduced. The RISC type microprocessor forms an instruction system with an instruction format of fixed 16-bit, 32-bit or 64-bit length wherein a simple process is performed by one instruction, whereby a relatively small number of instructions constitute the instruction system. Since the instruction is simple, the amount of required hardware of the control unit of the microprocessor is smaller than that of the CISC type microprocessor. Therefore this architecture is fit for pipeline processing and relatively easy to attain high-speed performance. An instruction format with a mixture of 16- and 32-bit length instructions constitutes the instruction system in some cases. Sun Microsystems"" SPARC and MIPS Technologies"" MIPS (e.g., R3000) are typical examples of the RISC processor.
In order to meet a growing demand for increasing operating speed, there has recently been employed a method of increasing the number of arithmetic units to be simultaneously operated in addition to the method of improving the operating frequency. The system for simultaneously operating a plurality of arithmetic units is called a superscalar system. However, the superscalar system needs the function of examining whether a plurality of instructions can simultaneously be executed, that is, the function of the instruction dependency and therefore the circuit scale tends to increase.
The VLIW type processor is a processor forming an instruction system with an instruction format of long instruction length though fixed length. In such a VLIW processor, a plurality of computing units are simultaneously operated by means of an instruction of 128 bits or longer. The number of computing units (the number of processing instructions executable in parallel) to be simultaneously operated is greater than that of the superscalar system. In the VLIW type processor, instruction dependency is checked beforehand at the time of compiling the source program and simultaneously executable instructions are combined into one instruction. When the number of simultaneously executable instructions does not reach the maximum number of simultaneously executable instructions, a NOP (No-operation) instruction is inserted by a compiler. The circuit scale of the VLIW type processor is smaller than that of the superscalar system of the RISC type microprocessor because the instruction dependency need not be checked at the time of execution of the VLIW type processor. Trace ce/300 of multiflow Computer Co. carried in Nikkei Electronics of Nov. 27, 1989 (No. 487), pp 196-197 is a typical example of the VLIW type processor.
The adoption of the RISC type architecture, for example, has improved operating frequency and increased the number of simultaneously executable instructions, thus resulting in improved performance of microprocessors. It has therefore been planned to use software for compression/expansion (MPEG (Moving Picture Experts Group) decoder/encoder) of moving pictures and three-dimensional graphic processing that have heretofore been done by using dedicated hardware or controllers.
The VLIW type microprocessor is thought to be fit for a processing for multimedia use dealing with a large quantity of data by repeating the same process including MPEG decoder/encoder and three-dimensional graphic processing.
A typical conventional microprocessor or a CPU (Central Processing Unit) is of a CISC or RISC type and possesses an accumulation of software assets. Microprocessors of the CISC, RISC and VLIW types each have different instruction sets, instruction formats, addressing modes, programming modes and the like; that is, no software compatibility exits.
There are limitations to improvement in the performance of a microprocessor having one of the above-described with the same architectures (including the instruction system). Thus, in order to improve performance the architecture of the microprocessor must be altered. However, altering the architecture of the microprocessor causes the problem to arise of compatibility with the accumulated software assets.
An object of the present invention is to provide a high-performance processor capable of executing software using a new architecture (instruction system) while maintaining compatibility with conventional software.
Another object of the present invention is to provide a high-performance processor capable of jointly processing or using resources in the processor such as arithmetic units so as to prevent an increase in the amount of required hardware.
Still another object of the present invention is to realize high-speed operation and low power consumption through a processor-to-processor operation control system.
The present invention provides a data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set and when the first processor executes a predetermined instruction of the first instruction set, the second processor executes an instruction of the second instruction set.
The data processor executes a program stored in a memory unit. The program includes a first program having instructions of a first instruction set and a second program having instructions of a second instruction set different from the first instruction set. The first and second programs are arranged in an address space of the data processor.
An instruction of the first instruction set has a variable length, whereas an instruction of the second instruction set has a fixed length. The maximum word length of an instruction of the first instruction set may be greater than the word length of an instruction of the second instruction set. The maximum word length of an instruction of the first instruction set may be shorter than the word length of an instruction of the second instruction set.
An instruction of the first instruction set and an instruction of the second instruction set may have a fixed length. The word length of an instruction of the first instruction set may be shorter than the word length of an instruction of the second instruction set.
The data processor includes a first data processing unit which has a plurality of computing units and is used for reading an instruction from a first memory which stores a first group of instructions and executing the instruction, a second data processing unit which has a plurality of computing units capable of parallel operation and is used for executing instructions simultaneously executable as one instruction, and a second memory for storing a group of instructions which the second data processing unit executes. When the instruction read by the first data processing unit is a predetermined instruction, an instruction to be executed by the second data processing unit is read from the second memory.
The present invention further provides a microprocessor which includes a RISC core for executing RISC instruction, a VLIW table for storing VLIW instructions, a VLIW core for executing a VLIW instruction, and a VLIW start decision unit for controlling operation switching between the RISC core and the VLIW core. When the RISC core executes a subroutine call or a branch instruction out of RISC instructions, a VLIW instruction is read from the VLIW table by use of a branch destination address and operation is transferred by the VLIW start decision unit from the RISC core to the VLIW core, whereby the VLIW instruction is caused to operate until a VLIW core completion code is read from the VLIW table.
The microprocessor further includes an address translation table translation-lookaside-buffer (TLB) for subjecting the branch destination address to address translation so that a signal for expanding the VLIW instruction read from the VLIW table may be read from the TLB simultaneously when the address translation is conducted.
The microprocessor even further includes a circuit for examining whether the operation of the VLIW instruction executed subsequent to a branch to the VLIW instruction is relevant to the operation of the RISC instruction which is restored after the execution of the VLIW instruction. The microprocessor is capable of executing the RISC instruction at the restoring destination in parallel without waiting for the completion of the VLIW instruction when no relevance exists.
The microprocessor includes a register for prohibiting and controlling the execution of the VLIW instruction in the processor and a function of lowering power consumption by causing a branch to a string of RISC instructions performing an operation equivalent to the VLIW instruction at the time the execution of the VLIW instruction is prohibited so as to suspend the operation of the VLIW core.
A non-volatile memory has a built-in VLIW table. The non-volatile memory is preferably one of a masked ROM, a flash memory and a ferroelectric memory. A volatile memory has a built-in VLIW table. The volatile memory of the VLIW table is preferably either SRAM or DRAM. A memory rewritable with the processor of the RISC core preferably has a built-in VLIW table.